DSOM-020 PX30 System on Module (SoM)

DSOM-020 PX30 System on Module/Core Board adopts the PX30 processor, which is a ARM Cortex A-53, quad core. It can be paired with multiple types of DDR3 and DDR4 RAM.
Table of Contents
dsom 020r front

1 DSOM-020 PX30 SOM Purpose & Description

1.1 System on Module Product Overview and Scope

The DSOM-020R PX30 Stamp Hole System on Module adopts PX30 industrial 64-bit lowpower processor with quad-core 64-bit Cortex-A35, frequency up to 1.3 GHz, supports multiple operating systems, with powerful hardware decoding capability and a rich interface. such as I2C, UART, SPI, SPIO 3.0, USB2.0, PWN, RMII, I2S(supports 8-way digital microphone array input) and others interfaces.

The DSOM-020R PX30K System on Module is suitable for industrial control, power, communication, medical, media, security, vehicle, finance, consumer electronics, handheld devices, game consoles, display control, teaching instruments, and many other fields. It can be widely used in POS systems, game machines, teaching experiment platforms, multimedia terminals, PDAs, food ordering machines, advertising machines, and other fields.

The DSOM-020R System on Module offers a wide range of development documents and software resources that are both free and open-source. This convenience enables developers to enhance their development efficiency and shorten the development cycle.

1.2 System on Module Features
  • Featuring a compact form factor and sufficient GPIO interfaces
  • Support for sleep/wake-up function
  • Using RK809 PMU for Power Management Power ensures stable and reliable operation while keeping costs low enough
  • Size 45mm*45mm
  • eMMC up to 32GB
  • RAM up to 2GB
  • Support power sleep and wake-up
  • Supports Buildroot, Linux + MiniGUI/QT, ROS
  • Supports 100M wired Ethernet
  • Leads out 144 PIN pins, including all CPU pins
  • RoHS certified
  • Stable and reliable product tested for high and low temperature, repeated reboot, Android stability, and AnTuTu benchmark
  • l Work continuously for 7 days and 7 nights without crashing (or failing).
1.3 System on Module Application
  • AIOT equipment
  • Vehicle control
  • Game equipment
  • Commercial display equipment
  • Medical equipment
  • Vending machines
  • Industrial computers

2 System Block Diagram of DSOM-020 PX30 SOM

2.1 Main Chip Block Diagram
px30k main chip block diagram
2.2 Core Board Block Diagram
px30 core board

3 Basic Parameters and Interfaces of DSOM-020 PX30 SOM

ItemParameter
CPUQuad-core 64-bit Cortex-A35, frequency up to 1.3 GHz
GPUEmbedded ARM G31-2EE GPU makes the PX30K fully compatible with OpenGL ES 1.1/2.0/3.2, DirectX 11 FL9_3, OpenCL 2.0, and Vulkan 1.0.
Built-in embedded high-performance 2D acceleration hardware
RAMLPDDR3 2GB (1GB optional)
StorageeMMC 32 GB (8GB / 16GB / 32GB /64GB / 128GB eMMC optional)
Power ManagementRK809-1 Dynamic adjustment of the output voltage of each DC-DC converter
Operating VoltageTypical voltage 5V/1.5A
RTC Input VoltageTypical voltage 5V/30 uA
OSAndroid / Debian
TemperatureOperating Temperature: -20 °C ~85 °C
Storage Temperature: -40 °C ~85 °C
Humidity10~95% (Non-condensing)
Barometric Pressure76Kpa ~ 106Kpa
Size45mm x 45mm x 2.6mm
ItemParameter
Ethernet1-channel 10M/100MHz Ethernet interface requires an external PHY chip
LCDSupport MIPI, LVDS, RGB Interface
TouchCapacitive touch can be expanded with USB or serial port resistive touch
AudioAC97 / IIS, Support recording and playback of audio
TF Card1 x SDIO Output Channel
I2S1 x 8-Channel I2S interface
SDIO1 x SDIO
eMMCOnboard eMMC interface, the pins are not additionally led out
USB 2.02-channel USB 2.0 interface, one of which is a USB OTG interface
UART6 x Serial Port, except for UART2, the other four channels support serial flow control
PWM8 x PWM Output
I2C4 x I2C
SPI2 x SPI
ADC3 x ADC
Camera1 x MIPI CSI camera input interface or parallel camera input interface.
UpgradeSupport local upgrade via USB interface.

4 Pin Definition of DSOM-020 PX30 SOM

dsom 020r front
Top Side Coreboard
dsom 020r back
Buttom Side Coreboard
PinPin DefinitionPad TypeI/O DefI/O Level (High/Low)
Unit: mA
I/O Driver
(Unit: V)
I/O Voltage
(Unit: V)
Functions
1GPIO0_A5I/OIup23.0GPIO0_A5
2GPIO0_C2/I2C1_S
C L/UART3_CTS
I/OIdown23.0GPIO or I2C pins or UART 3 flow control pin
3GPIO0_C2/I2C1_S
C L/UART3_CTS
I/OIdown23.0GPIO or I2C pins or UART 3 flow control pin
4GPIO0_B4/UART0
_ CTS
I/OIup23.0GPIO or UART 0 flow control pin
5GPIO0_C0/PWM1
/ UART3_TXD
I/OI/Odown23.0GPIO or UART 3 TXD or PWM pin
6VCC3V3_LCDPN/AN/A3.3V/2.5A power output
7LVDS_TX0N/MIPI
_T
X_D0N/LCDC_D1
1_ M1
AN/A3.3LCD Driver Interface
........................

NOTE:
I/O types: I = digital-input, O = digital-output, I/O = digital input/output (bidirectional)
A=Analog IO
Def default IO direction for digital IO
All GPIO pins support interrupts. P = power supply
VCC3V3_SYS, VCC3V0_PMU It is best not to supply power to these power outputs. They can be used as pull-up power supplies

5 Electrical Parameters of DSOM-020 PX30 SOM

5.1 Absolute Electrical Parameters
ParameterDescriptionMinTypMaxUnit
VCC5V0_SYS(_1/_2/_3)VCC5V0_SYS Input voltage-0.36.5V
VCC_IO_RTCRTC Input Voltage-0.36.5V
TaOperating temperature range-2085
TsStore temperature range-4085

Note:
Exposure to conditions beyond the absolute maximum ratings may cause permanent damage and affect the reliability and safety of the device and its systems.
The functional operations cannot be guaranteed beyond specified values in the recommended conditions.

5.2 Normal working parameters
ParameterDescriptionMinTypMaxUnit
VCC5V0_SYSVCC5V0_SYS Input Voltage4.7555.5V
VCC_RTCRTC Input Voltage4.7555.5V
VCC5V0_SYS Supply CurrentVCC5V0_SYS Input Current1A
VCC_RTC Supply Current30uA
TaOperating temperature-202585
TsStore temperature range-402585

6 Hardware Design Guidelines of DSOM-020 PX30 SOM

6.1 SPI Controller

The PX30K chip has two SPI controllers that can be used to connect SPI devices.
The recommended pull-up/pull-down and matching design for the SPI interface is shown in the table below

SignalInternal pull
up/down
Connection methodDescription
SPI0_MOSIPull-downDirect ConnectionSPI data transmission
SPI0_MIS0Pull-upDirect ConnectionSPI data reception
SPI0_CLKPull-upSeries with 22ohm resistorSPI clock transmission
SPI0_CSNPull-upDirect ConnectionSPI Slave Select Signal
6.2 SDMMC Interface

The PX30K chip provides an SDMMC interface controller that supports SD v3.0 and MMCv4.51 protocols. The recommended pull-up/pull-down and matching design for the SDMMC interface are shown in the table below

SignalInternal pull
up/down
Connection method
(SDRHigh-Speedpeed Mode )
Description
SDMMC1_DQ[3:0]Pull-upSeries with 22ohm resistor
When the trace is short, it can be deleted
SD data
transmission / reception
SDMMC1_CLKPull-downSeries with 22ohm resistorSD clock transmission
SDMMC1_CMDPull-upSeries with 22ohm resistor
When the trace is short, it can be deleted
SD command
transmission/reception
6.3 USB Interface

The PX30K chip has two sets of USB 2.0 interfaces, one supporting OTG mode and the other acting as a host. Please note the following when designing:

  • USB interfaces are used as the default system firmware burning ort, and must
    be reserved when designing.
  • USB_ID has a 200K internal pull-up resistor, which is pulled up to
  • USB_AVDD_1V8, so OTG is set to Device mode by default.
  • USB_DET (USB_VBUS) is used for USB insertion detection, and when it detects a high level, it means that USB has been inserted.
  • To suppress electromagnetic radiation, it is recommended to reserve a common mode choke on the signal line. During debugging, use a resistor or common mode choke as appropriate.
SignalConnection MethodDescription
USB_OTG_DP/DMDirect ConnectionUSB OTG input/output
USB_IDDirect Connection( Internal pull up)USB OTG ID recognition, used for Micro-B interface
USB_DETUSB OTG insertion detection

USB2.0 signal design rules:

  • The intra-pair skew of differential pairs is less than 2ps;
  • The length of differential pairs is less than 3 inches;
  • The number of vias for differential pairs to change layers is less than 3;
  • The impedance of differential pairs is controlled within 90ohm+/-10%;
  • The spacing between differential pairs and other signals follows the 3W principle.
6.4 Audio Interface

PX30K provides three standard I2S interfaces, all supporting master and slave modes with a maximum sampling rate of 192kHz and a bit rate ranging from 16 bits to 32 bits.

I2S0
The I2S0 interface of the PX30K provides the independent 8-channel output and 8- channel input. To meet the needs of asynchronous sampling rates for playback and recording, two sets of bit clocks and frame clocks (SCLKTX/ LRCKTX, SCLKRX/ LRCKRX) are also provided. It should be noted that for the case where only one set of bit/frame clocks is referenced for SDOx and SDIx, SCLKTX/LRCKTX is preferred as their standard clock.

SignalInternal pull
up/down
Connection methodDescription
I2S0_8CH_MCLKPull-downSeries with 22ohm resistorI2S0 System clock output
I2S0_8CH_SCLKTXPull-downSeries with 22ohm resistorI2S0 Bit clock (TX, Associated with SDOx)
I2S0_8CH_LRCKTXPull-downSeries with 22ohm resistorI2S0 Frame clock output for channel selection clock ( TX, Associated with SDOx)
I2S0_8CH_SDO0Pull-downSeries with 100ohm resistorI2S0 Data output channel 0
I2S0_8CH_SDO1Pull-downSeries with 22ohm resistorI2S0 Data output channel 1
I2S0_8CH_SDO2Pull-downSeries with 22ohm resistorI2S0 Data output channel 2
I2S0_8CH_SDO3Pull-downSeries with 22ohm resistorI2S0 Data output channel 3
I2S0_8CH_SCLKRXPull-downSeries with 100ohm resistorI2S0 Bit clock (RX, Associated with SDIx)
I2S0_8CH_LRCKRXPull-downSeries with 22ohm resistorI2S0 Frame clock output for channel selection clock ( RX, Associated with SDIx)
I2S0_8CH_SDI0Pull-downSeries with 22ohm resistorI2S0 Data output channel 0
I2S0_8CH_SDI1Pull-downSeries with 22ohm resistorI2S0 Data output channel 1
I2S0_8CH_SDI2Pull-downSeries with 100ohm resistorI2S0 Data output channel 2
I2S0_8CH_SDI3Pull-downSeries with 22ohm resistorI2S0 Data output channel 3

I2S1
I2S1 supports 2-channel input and 2-channel output. The pull-up and matching design recommendations for the I2S1 interface are shown in the following table.

SignalInternal pull
up/down
Connection methodDescription
I2S1_MCLKPull downSeries with 22ohm resistorI2S1 System clock output
I2S1_SCLKPull downSeries with 22ohm resistorI2S1 Bit clock output
I2S1_LRCK_TXRXPull downSeries with 22ohm resistorI2S1 Frame clock output for channel selection clock
I2S1_SDOPull downSeries with 22ohm resistorI2S1 Data output channel
I2S1_SDIPull downSeries with 22ohm resistorI2S1 Data input channel

I2S2
I2S2 supports 2-channel output and 2-channel input and is used by default to connect to the PCM interface of the BT module, serving as the communication port for the Bluetooth call function under the HFP protocol.
The recommended pull-up and matching design for the I2S2 interface is shown in the following table.

SignalInternal pull
up/down
Connection methodDescription
I2S2_2CH_MCLKPull downSeries with 22ohm resistorI2S0_2CH system clock output
No PCM function multiplexing can be used as a normal GPIO
I2S2_2CH_SCLK
PCM_CLK
Pull downSeries with 22ohm resistorI2S0_2CH bit clock output
PCM clock
I2S2_2CH_LRCK
PCM_SYNC
Pull downSeries with 22ohm resistorI2S0_2CH Frame clock output for channel selection clock
PCM Data frame synchronisation
I2S2_2CH_SDO
PCM_OUT
Pull downSeries with 22ohm resistor2S0_2CH Data output channel
PCM data output
I2S2_2CH_SDI
PCM_IN
Pull downSeries with 22ohm resistor2S0_2CH Data input channel
PCM data Input

PX30K provides one set of PDM digital audio interfaces, supporting up to 8 channels of PDM format audio input with a maximum sampling rate of 192kHz and bit rates ranging from 16bits to 32bits.

To cooperate with RK809-1 to achieve audio input, the IO multiplexing here is relatively flexible, and care should be taken to avoid repeated use of the same signal in different multiplexing positions. When using PDM MIC as voice input, to simplify the software processing of audio recording data, it is recommended to use the PDM interface consistently for both recording and input. This way, for the common application scenarios involving 2-6 PDM MIC recording channels and 1-2 channels of input, only one complete 4-8 channel recording audio is needed, and no extra splicing processing is required in the software.

If you need to connect 8-channel PDM MIC input, you can only use the I2S interface as the capture channel for input. Software needs to perform additional audio splicing processing to meet the requirements of the algorithm for data synchronization.

Codec

RK809-1 comes with a codec and is connected to PX30K via the I2S interface. The HPSNS output of the codec serves as an internal offset reference and needs to be connected to GND. The routing should be connected to GND at the headphone jack to reduce the potential difference between the codec and the headphone GND. If the codec’s GND is on the same complete GND plane as the headphone GND and the device layout is close, it can be directly connected to the GND plane.

The codec has a built-in mono non-filtered speaker driver circuit that can provide 1.3W@8ohm of driving power, which meets the application requirements of small power monaural scenarios and can save additional external amplifier costs. When using this built-in amplifier, the recommended audio input circuit is as follows: after voltage division and filtering, the differential feedback signal is output to the audio ADC interface of RK809-1 and then passed back to PX30K through the PDM/I2S interface after A/D conversion by RK809-1.

The default setting for RK809-1 here is PDM interface communication with PX30K, which is based on the consideration of using PDM microphones, as described in the PDM interface section.

px30k speaker circuit
PX30K Speaker Circuit

MIC

The MIC circuit is shown in the following diagram. Please select appropriate voltage divider resistors R7105 and R7106 according to the specifications of the electret microphone. If an analog interface MEMS MIC is used, please refer to the specifically recommended design circuit. If a digital interface MEMS MIC is used, it can be directly connected to the I2S0 of PX30K.

px30 mic
6.5 Video Interface

Video Interface The PX30K chip has a built-in video controller that supports three video output modes: RGB, LVDS, and MIPI DSI.

LVDS/MIPI Mode 
LVDS/MIPI uses the same controller, and some pins are shared with RGB. When using LVDS/MIPI output, the software needs to configure the corresponding output mode.

LVDS/MIPI signal design rules:

  • Differential pair offset within 2ps.
  • The differential pair group offset between Clk and Data is less than 3.5ps.
  • The differential pair length is less than 3.6 inches.
  • The number of through-holes for differential pairs to change layers is less than 3.
  • Differential pair impedance is controlled within 100ohm+/-10%.
  • The distance between differential pairs and other signals follows the 3W
    principle.

RGB Mode
PX30K supports 24-bit RGB output. When using RGB output, the software needs to configure the corresponding output mode.
When using an RGB888 24-bit screen, the corresponding signal relationship is as follows:

rgb mode

When using an 18-bit RGB666 screen, only the LCDC_D0-D17 data signals need to be connected, and the corresponding signal relationship is as follows:

6.6 Camera Interface

MIPI CSI
PX30K has a MIPI-CSI input with a built-in ISP processor.
MIPI signal design rules:

  • Differential pair offset within 2ps.
  • The differential pair group offset between Clk and Data is less than 3.5ps.
  • The differential pair length is less than 3.6 inches.
  • The number of through-holes for differential pairs to change layers is less than 3.
  • Differential pair impedance is controlled within 100ohm+/-10%.
  • The distance between differential pairs and other signals follows the 3W principle.

CIF CAMERA
The power supply domain for the CIF interface is 3.0V. In the actual product design, the corresponding power supply should be selected based on the actual IO power supply requirements of the camera (1.8V or 2.8V), and the I2C pull-up voltage level must be consistent with it. Otherwise, it will cause the camera to malfunction or not work. The CIF interface pins are multiplexed with the RMII pins.

RMII Circuit
The RMII and CIF interfaces can be multiplexed and configured to support 100Mbps Ethernet PHY, enabling the implementation of 100Mbps network functionality. Please refer to the PHY manufacturer’s design documentation for details on designing a 100Mbps network. The clock signal required by the PHY can be generated by an external crystal or provided by the chip’s MAC_CLK signal.

rmii circuit
6.7 ADC Interface

The PX30K chip uses the SARADC’s ADC_IN2 as the key input sampling port and also for RECOVER mode (which does not require updating LOADER). With the firmware already burned into the system, pulling ADKEY_IN low during system startup will keep ADC_IN2 at a 0V level, allowing PX30K to enter the Rockusb firmware writing mode. When the PC recognizes the USB device, release the button to restore ADC_IN2 to a high level (1.8V), and then the firmware writing can be carried out.

On PX30K, the SARADC sampling range is 0-1.8V, and the sampling accuracy is 10 bits. The parallel-type key array can adjust the input key value by adding or reducing keys and adjusting the voltage divider ratio to achieve multi-key input to meet customer product requirements. In design, it is recommended that any two key values must be greater than +/- 35, which means that the center voltage difference must be greater than 123 mV.The pull-up and matching design recommended for the SDIO1 interface is shown in the following table.

6.8 SDIO/UART Interface

PX30K supports WIFI/BT modules with SDIO 3.0 interface. When using WIFI/BT modules with SDIO1 and UART interfaces, it is important to ensure that the power supply of PX30K’s SDIO1 and UART1 controllers is consistent with the IO level of the module.

SDI0

The recommended pull-up/down and matching design for the SDMMC0 interface are as follows:

Signal IInternal pull
up/down
Connection methodDescription
SDI0_DQn[3:0]Pull UpSeries with 22ohm resistor
The routing can be removed temporarily for shorts
SDI0 data transmission and reception
SDI0_CLKPull DownSeries with 22ohm resistorSDI0 clock signal transmission
SDI0_CMDPull DownSeries with 22ohm resistor
The routing can be removed temporarily for shorts
SDI0 data transmission and reception

UART

The recommended pull-up/down and matching design for the SDMMC1 interface are as follows:

SignalInternal pull
up/down
Connection methodDescription
UART1_RXPull upDirect ConnectionUART1 Data input
UART1_TXPull upDirect ConnectionUART1 Data output
UART1_CTSnPull upDirect ConnectionUART1 allows signal transmission
UART1_RTSnPull upDirect ConnectionUART1 requests signal transmission

7 Product Dimensions of DSOM-020 PX30 SOM

px30k dimensions
ItemParameter
ExteriorStamp Hole
Core Board Size45mm x 45mm x 2.6mm
Pin Spacing1.2mm
Pin Pad Size2.0mm x 0.7mm
Number of Pins144 Pins
Warpageless than 0.5 %

8 The methods of Coreboard Thermal Control

8.1 Thermal Control Strategy

There is a generic thermal system driver framework in the Linux kernel that defines a number of temperature control strategies. The following three strategies are currently in common use:

  • Power_allocator: Introduces proportional-integral-derivative (PID) control,
    dynamically allocates power to each module based on the current temperature,
    and converts power to frequency to achieve frequency limiting based on
    temperature.
  • Stepwise: Limits the frequency of steps based on the current temperature.
  • User space: Does not limit frequency.

The RK3568 chip has a T-sensor that detects the chip’s internal temperature and uses the Power_allocator strategy by default. The operating states are as follows:

  • If the temperature exceeds the set temperature value:
    – If the temperature trend is rising, the frequency is gradually reduced.
    – If the temperature trend is falling, the frequency is gradually increased.
  • When the temperature falls to the set temperature value:
    – If the temperature trend is increasing, the frequency remains unchanged.
    – If the temperature trend is falling, the frequency is gradually increased.
  • If the frequency reaches its maximum and the temperature is still below the set value, the CPU frequency is no longer under thermal control, and the CPU frequency becomes system load frequency modulation.
  • If the chip is still overheating after the frequency has been reduced (e.g., due to poor heat dissipation) and the temperature exceeds 95 degrees, the software will trigger a restart. If the restart fails due to deadlock or other reasons and the chip exceeds 105 degrees, the otp_out inside the chip will trigger a direct shutdown by the PMIC.

Note: The temperature trend is determined by comparing the previous and current temperatures. If the device temperature is below the threshold, the temperature is sampled every l seconds; if the device temperature exceeds the threshold, the temperature is sampled every 20ms, and the frequency is limited. 

The RK3568 SDK provides separate thermal control strategies for the CPU and GPU. Please refer to the (Rockchip_Developer_Guide_Thermal) document for specific configurations.

9 Production Guide of DSOM-020 PX30 SOM

9.1 SMT process

Select modules that can be SMT or in-line packaged according to the customer’s PCB design scheme. If the board is designed for SMT packaging, use SMT-packaged modules. If the board is designed for in-line assembly, use in-line assembly.

Modules must be soldered within 24 hours of unpacking. If not, place them in a dry cabinet with a relative humidity of no more than 10% or re-pack them in a vacuum and record the exposure time (total exposure time must not exceed 168 hours).

Instruments or equipment required for SMT assembly:

  • SMT Mounter
  • SPI
  • Reflow soldering
  • Oven temperature tester
  • AOI

Instruments or equipment required for baking:

  • Cabinet ovens
  • Antistatic high-temperature trays
  • Antistatic and high-temperature gloves
9.2 Module storage conditions:

Moisture-proof bags must be stored at a temperature <40°C and humidity <90% RH. Dry-packed products have a shelf life of 12 months from the date of sealing of the package. Sealed packaging with humidity indicator card.

humidity indicator card
9.3 Baking is required when:

The vacuum bag is found to be broken before unpacking.

After unpacking, the bag is found to be without a humidity indicator card. The humidity indicator card reads 10% or more after unpacking, and the color ring turns pink.

Total exposure time after unpacking exceeds 168 hours. More than 12 months from the date of the first sealed packaging.

Baking parameters are as follows:
Baking temperature: 60°C for reel packs, humidity less than or equal to 5% RH; 125°C for tray packs, humidity less than or equal to 5% RH (high-temperatureresistant trays, not blister packs for tow trays).

Baking time: 48 hours for reel packaging; 12 hours for pallet packaging.

Alarm temperature setting: 65°C for reel packs; 135°C for pallet packs.

After cooling to below 36°C under natural conditions, production can be carried out.

If the exposure time after baking is greater than 168 hours and not used up, bake again.

If the exposure time is more than 168 hours without baking, it is not recommended to use the reflow soldering process to solder this batch of modules. The modules are class 3 moisture-sensitive devices and may become damp when the exposure time is exceeded.

This may lead to device failure or poor soldering when hightemperature soldering is carried out.

9.4 ESD

Please protect the module from electrostatic discharge (ESD) during the entire production process.

9.5 Conformity

To ensure product qualification rates, it is recommended to use SPI and AOI test equipment to monitor solder paste printing and placement quality.

9.6 Recommended Furnace Temperature Profile

Please follow the reflow profile for SMT placement with a peak temperature of 245°C. The reflow temperature profile is shown below using the SAC305 alloy solder paste as an example.

graphs curves

Description for graphs of curves.
A: Temperature axis
B: Time axis
C: Alloy liquid phase line temperature: 217-220°C
D: Slope of temperature rise: 1-3°C/s
E: Constant temperature time: 60-120s, constant temperature: 150-200°C
F: Time above liquid phase line: 50-70s
G: Peak temperature: 235-245°C
H: slope of temperature reduction: 1-4°C/s
Note: The above recommended curves are based on SAC305 alloy solder paste as an example. Please set the recommended oven temperature curve for other alloy solder pastes according to the solder paste specification.

9.7 Storage
storage
9.8 Order Information
ModelRAMeMMC
DSOM-020R-K1GB8GB
DSOM-020R-N2GB32GB
DSOM-020R-P2GB128GB

Documentations

DusunIoT offers full set of development resources including QUICK START, SDK, Firmware packaging, module firmware, Tools, vairous third party software,etc.

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