DSOM-050 RK3308 System on Module

DSOM-050 RK3308 System on Module (SoM) / Core Board adopts an IoT-focused processor with a quad-core 64-bit Cortex-A35 architecture that can run at a maximum frequency of 1.3Ghz. It can be paired with DDR3 and DDR3L RAM.
Table of Contents
DSOM 050 RK3308

1 DSOM-050 RK3308 SOM Product Description

1.1 Product Overview and Scope

DSOM-050R RK3308B System on Module adapts 136 pin stamp hole design and is equipped with RK3308B, an IoT-focused processor with a quad-core 64-bit Cortex-A35 architecture that can run at a maximum frequency of 1.3Ghz. It boasts an integrated high-performance Codec and hardware VAD (Voice Activation Detection) and is compatible with a variety of operating systems, speech systems, and services.

Additionally, it offers numerous expansion interfaces and powerful display drive capabilities, making it a versatile choice for IoT applications, including smart speakers and displays, that demand advanced audio processing and speech recognition capabilities.

The DSOM-050R RK3308B System on Module offers a wide range of development documents and software resources that are both free and open-source. This convenience enables developers to enhance their efficiency and shorten the development cycle. Video streams and high quality audio streams – perfect for commercial/industrial applications that will have customer and public facing software.

1.2 System on Module Features
  • Featuring a compact form factor and sufficient GPIO interfaces
  • Size 45mm*40.2mm
  • eMMC up to 128GB
  • RAM up to 512MB DDR3
  • Support power sleep and wake-up
  • Supports Buildroot, Linux + MiniGUI/QT, ROS
  • Supports 100M wired Ethernet
  • Leads out 136 PIN pins, 1.2mm pitch, including all CPU pins
  • RoHS certified
1.3 System on Module Application
  • lIoT Gateways
  • Smart Speakers
  • Smart Displays
  • Voice Assistants
  • Healthcare
  • Industrial Control

2 System Block Diagram of DSOM-050 RK3308 SOM

2.1 Main Chip Block Diagram
image2
2.2 System on Module Block Diagram
image3

3 Basic Parameters and Interfaces of DSOM-050 RK3308 SOM

Item Parameter
CPU Quad-Core ARM® Cortex-A35 64-bit processor, Frequency up   to
     1.3GHz
RAM 512 MB DDR3/LPDDR3 (128MB/ 512MB optional)
Storage eMMC 8 GB (4GB / 8GB / 16GB / 32GB/ 64G / 128G eMMC
     optional)
Power Management Isolated DC/DC Converters that support dynamic frequency
     scaling
Operating Voltage Typical voltage 5V/0.5A
OS Buildroot, Linux + MiniGUI/QT, ROS (Robot Operating System)
Temperature Operating Temperature: -10°C ~60 °C
Storage Temperature:   -40 °C ~85 °C
Humidity 10~95%(Non-condensing)
Barometric Pressure 76Kpa ~106Kpa
Size 45mm×40.2mm x 3.35mm
Item Parameter
Ethernet 1 X 10M/100MHz RMII Ethernet interface needs an external PHY chip
LCD Parallel RGB LCD interface supports RGB888, ARGB888, RGB565, YCbCr422, YCbCr420, YCbCr444
Audio The system provides a rich set of digital and analog audio interfaces, including support for I2S, PDM, TDM, and SPDIF.
● built-in stereo headphone and line-out outputs and support for up to six channels of analog microphone input
● supports 8-channel I2S/TDM x 2, 8-channel PDM, and 2-channel I2S/PCM.
● supports up to 8-channel microphone array with echo cancellation
UART 5 X Serial Ports and flow control are supported on all four channels except for UART2
I2C 4 x I2C
SDIO 1 x SDIO
SPI 1 x SPI
PWM 11 x PWM output, including multiplexed channels
USB 2.0 2 x USB2.0, one of which is for OTG
USB 3.0 1 x USB3.0
Ethernet the main chip integrates a 100M Ethernet chip
TF 1 x SDIO
GPIO Defined features
ADC 6 x ADC
Upgrade supports local firmware upgrades via USB interface

4 Pin Definition of DSOM-050 RK3308 SOM

2q234 01

Top Side Coreboard

2q234 02

Buttom Side Coreboard

Pin Name I/O Type I/O level (High / Low) I/O Def I/O Voltage (Unit: V) Function
1 GND7 G / GND GND power ground
2 GND8 G / GND GND power ground
3 GND9 G / GND GND power ground
4 VCC5V0_SYS_1 P / power 5 System power supply input voltage: minimum 4.8V, typical 5V, maximum 5.5V
Input current: 500mA typical, 1000mA maximum
5 VCC5V0_SYS_2 P / power 5
6 VCC5V0_SYS_3 P / power 5
7 VCC_IO_1 P / power 3.3 DC-DC output voltage 3.3V, maximum output current 500mA
8 VCC_IO_2 P / power 3.3
9 VCC_1V8 P / power 1.8 LDO output voltage 1.8V, maximum output current 100mA
10 GPIO0_A6_d_3.3V I/O DOWN I/GPIO 3.3 Power LED driver enables (output) 1: Enable 0: Disable
11 GPIO0_B0_d_3.3V I/O DOWN I/GPIO 3.3 MIC array LED drive enable (output) 1: Enable 0: Disable
...

NOTE:
I/O types: I = digital-input, O = digital-output, I/O = digital input/output (bidirectional),
A=Analog O. Def default IO direction for digital IO.
I/GPIO = When used as GPIO port, it is input (I).
P = power supply G = GND.
VCC_IO_1, VCC_IO_1, VCC_1V8 It is best not to supply power to these power output pins. They can be used as pull-up power supplies.

5 Eletronical Parameters of DSOM-050 RK3308 SOM

5.1 Absolute Electrical Parameters
Parameter Description Min Typ Max Unit
VCC5V0_SYS (_1/_2/_3) VCC5V0_SYS Input voltage -0.3   6.0 V
VCC_IO_1
VCC_IO_2
3.3V IO out voltage -0.3   3.6 V
VCC_1V8 1.8V IO out voltage -0.3   2.1 V
Ta Operating temperature range -10   60 °C
Ts Store temperature range -40   85 °C

Note: Exposure to conditions beyond the absolute maximum ratings may cause permanent damage and affect the reliability and safety of the device and its system.  The functional operations cannot be guaranteed beyond specified values in the recommended conditions.

5.2 Normal working parameters
Parameter Description Min Typ Max Unit
VCC5V0_SYS (_1/_2/_3) VCC5V0_SYS Input voltage 4.8 5 5.2 V
VCC_IO_1 VCC_IO_2 3.3V IO out voltage 3.0 3.3 3.4 V
VCC_1V8 1.8V IO out voltage 1.7 1.8 1.9 V
VCC5V0_SYS Supply VCC5V0_SYS Input current     0.3 A
Ta Operating temperature range -10 25 60 °C
Ts Storage temperature range -40 25 85 °C

6 Hardware Design Guidelines

6.1 Analog Audio Interface

RK3308B has rich analog audio interfaces, including 8 channels of ADC inputs and 2 channels of DAC outputs, which contain 8 channels of MIC In interfaces, 2 channels of HP Out interfaces, and 2 channels of Line Out interfaces

DSOM 050R channels
Analog Audio Interface
DSOM 050R analog
Analog MIC Interface

In the design of microphone array products, to facilitate software transplantation and maintenance, the allocation of microphone input channels and speaker return channels should follow the configuration table suggested by our company. For instance, in the 6 microphone inputs + 2 speaker outputs scheme, MIC3 to MIC8 are allocated as analog microphone input channels, while MIC1 to MIC2 are used as return channels.

The RK3308B has two MICBIAS outputs, and each MICBIAS can provide a 3mA current. For optimal performance, it is recommended to distribute the two MICBIAS power supplies among the microphones equally. If 6 analog microphones are used in the product, each MICBIAS can supply power to 3 microphones.

Application Scene MIC IN Channel Loopback Channel
6MIC IN + 2Speaker OUT MIC3~MIC8 MIC1~MIC2
6MIC IN + 1Speaker OUT MIC3~MIC8 MIC1
5MIC IN + 2Speaker OUT MIC4~MIC8 MIC1~MIC2
5MIC IN + 1Speaker OUT MIC4~MIC8 MIC3
4MIC IN + 2Speaker OUT MIC5~MIC8 MIC3~MIC4
4MIC IN + 1Speaker OUT MIC5~MIC8 MIC3
3MIC IN + 1Speaker OUT MIC6~MIC8 MIC5
2MIC IN + 1Speaker OUT MIC7~MIC8 MIC5
Microphone and Return Channel Allocation Table
6.1.1 Line Out

The RK3308 comes with a set of DAC Line Outs output pins, which are mainly used to connect to an external power amplifier as a signal input, as shown in the following Figure:

dsom 050r line out
6.1.2 HP Out

RK3308’s HP Out is connected to the headphones with an insertion detection function. The circuit diagram is shown below. When the headphones are inserted, the PHONE_DET signal changes from low level to high level (the high-level value is 1.8V), the headphone detection register value is set to 0x01, and the interrupt system responds to the headphone insertion.

dsom 050r hp out
RK3308 HP Out Interface
dsom 050 line out hp out
Line OUT/HP OUT/MIC Circuit
6.2 Digital Audio Interface
6.2.1 I2S Digital Audio Interface

RK3308B provides three sets of standard independent I2S interfaces, namely I2S0_2CH, I2S0_8CH, and I2S1_8CH, all of which support Master or Slave mo e. The highest supported sampling rate of the I2S interface is up to 192KHz, and the resolution can be supported from 16-bit to 32-bit.

rk3308 i2s0 8ch module
RK3308 I2S0_8CH Module

As shown in the Figure, the I2S0_8CH interface includes independent 8-channel inputs and 8-
channel outputs. To meet playback and recording requirements with different sampling rates, two sets of bit clocks and frame clocks are provided correspondingly (SCLK_TX/LRCK_TX,
SCLK_RX/LRCK_R). By default, the input channel SDIx corresponds to SCLK/LRCK_RX, and the output channel SDOx corresponds to SCLK_TX/LRCK_ X. For SD0x and SDIx, only one set of bit/frame clocks is referred to, and SCLK_TX/LRCK_TX is given priority as their common clock.

Signal Internal Pull up/Down Connection Method Description
I2S0_8CH_MCLK Pull Down Series with 22ohm resistor I2S0_8CH system clock output
I2S0_8CH_ SCLK_TX Pull Down Series with 22ohm resistor I2S0_8CH bit clock output(TX,Associated with SDOx)
I2S0_8CH_ SCLK_RX Pull Down Series with 22ohm resistor Master: I2S0_8CH bit clock output(RX, Associated with SDIx)
Slave: I2S0_8CH bit clock input
I2S0_8CH_ LRCK_TX Pull Down Series with 22ohm resistor I2S0_8CH Frame clock output for channel selection clock output (T X, Associated with SDOx)
I2S0_8CH_ LRCK_RX Pull Down Series with 22ohm resistor I2S0_8CH Frame clock for Sound channel selection
Maste r:I2S0_8CH clock output (RX, Associated with SDIx)
Slave: I2S0_8CH bit clock input
I2S0_8CH_SDI0 Pull Down Series with 22ohm resistor I2S0_8CH Data input channel 0
RK3308 I2S0_8CH Interface Design
Signal Internal Pull up/Down Connection Method Description
I2S0_8CH_SDI1 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 1
I2S0_8CH_SDI2 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 2
I2S0_8CH_SDI3 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 3
I2S0_8CH_SDO0 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 0
I2S0_8CH_SDO1 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 1
I2S0_8CH_SDO2 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 2
I2S0_8CH_SDO3 Pull Down Series with 22ohm resistor I2S0_8CH data input channel 3
I2S0_8CH Configuration

I2SO_2CH
I2S0_2CH supports 2-channel input and 2-channel output and is used by default to connect the PCM interface of the BT module as a communication port for the Bluetooth call function under the HFP protocol.

rk3308 i2s0 2ch module
RK3308 I2S0_2CH Module
Signal Internal Pull up/Down Connection Method Description
I2S0_2CH_MCLK Pull Down Series with 22ohm resistor I2S0_2CH system clock output
No PCM function multiplexing can be used as a normal GPIO
I2S0_2CH_ SCLK Pull Down Series with 22ohm resistor I2S0_2CH bit clock output
PCM clock
I2S0_2CH_ LRCK_TX Pull Down Series with 22ohm resistor I2S0_2CH Frame clock output for channel selection clock
PCM Data frame synchronisation
I2S0_2CH_SDI Pull Down Series with 22ohm resistor I2S0_2CH Data input channel
PCM data input
I2S0_2CH_SD0 Pull Down Series with 22ohm resistor I2S0_2CH Data input channel
PCM data output
I2S0_2CH Configuration

The I2S1_8CH interface contains 1 SDI0, 1 SDO0, and 3 SDIxSDOx interfaces, so the SDIx and SDOx interfaces can be flexibly configured. It can support 8-channel input/2-channel output or 8-channel output/2-channel input simultaneous y. To meet the needs of playback and recording with different sampling rates, two sets of bit clock and frame clock are provided (SCLK_TX/LRCK_TX, SCLK_RX/LRCK_RX) corresponding y. The default input channel SDIx corresponds to SCLK_RX/LRCK_RX, and the output channel SDOx corresponds to SCLK_TX/LRCK_ X. For SDOx and SDIx, when considering only one set of bit/frame clocks, SCLK_TX/LRCK_TX is given priority as their common clock.

rk3308 i2s1 8ch module
RK3308 I2S1_8CH Module
Signal Internal Pull up/Down Connection Method Description
I2S1_8CH_MCLK_M0 Pull Down Series with 22ohm resistor I2S1_8CH system clock output
I2S1_8CH_ SCLK_TX_M0 Pull Down Series with 22ohm resistor I2S1_8CH bit clock output (TX,Associated with SDOx)
I2S1_8CH_ SCLK_RX_M0 Pull Down Series with 22ohm resistor Master: I2S1_8CH bit clock output (RX, Associated with SDIx)
Slave: I2S1_8CH bit clock input
I2S1_8CH_ LRCK_TX_M0 Pull Down Series with 22ohm resistor I2S1_8CH Frame clock output for channel selection clock output ( TX, Associated with SDOx)
I2S0_8CH_ LRCK_RX_M0 Pull Down Series with 22ohm resistor I2S0_8CH Frame clock for Sound channel selection
Master: I2S1_8CH clock output (RX, Associated with SDIx)
Slave: I2S1_8CH Frame clock input
I2S0_8CH_SD00_M0 Pull Down Series with 22ohm resistor I2S1_8CH Data input channel 0
I2S0_8CH_SD01SDI3_M0 Pull Down Series with 22ohm resistor I2S1_8CH Data output channel 1/ input channel 3
I2S0_8CH_SD01SDI2_M0 Pull Down Series with 22ohm resistor I2S1_8CH Data output channel 2/ input channel 2
I2S0_8CH_SD01SDI1_M0 Pull Down Series with 22ohm resistor I2S1_8CH Data output channel 3/ input channel 1
I2S0_8CH_SDI0_M0 Pull Down Series with 22ohm resistor I2S1_8CH Data input channel 0
I2S1_8CH
I2S1_8CH_MCLK_M1 Pull Down Series with 22ohm resistor I2S1_8CH system clock output
I2S1_8CH_ SCLK_TX_M1 Pull Down Series with 22ohm resistor I2S1_8CH bit clock output(TX,Associated with SDOx)
I2S1_8CH_ SCLK_RX_M1 Pull Down Series with 22ohm resistor Master: I2S1_8CH bit clock output(RX, Associated with SDIx)
Slave: I2S1_8CH bit clock input
I2S1_8CH_ LRCK_TX_M1 Pull Down Series with 22ohm resistor I2S1_8CH Frame clock output for channel selection clock output (TX, Associated with SDOx)
I2S0_8CH_ LRCK_RX_M1 Pull Down Series with 22ohm resistor I2S0_8CH Frame clock for Sound channel selection
Master:I2S1_8CH clock output (RX, Associated with SDIx)
Slave: I2S1_8CH Frame clock input
I2S0_8CH_SD00_M1 Pull Down Series with 22ohm resistor I2S1_8CH Data input channel 0
I2S0_8CH_SD01SDI3_M1 Pull Down Series with 22ohm resistor I2S1_8CH Data output channel 1/ input channel 3
I2S0_8CH_SD01SDI2_M1 Pull Down Series with 22ohm resistor I2S1_8CH Data output channel 2/ input channel 2
I2S0_8CH_SD01SDI1_M1 Pull Down Series with 22ohm resistor I2S1_8CH Data output channel 3/ input channel 1
I2S0_8CH_SDI0_M1 Pull Down Series with 22ohm resistor I2S1_8CH Data input channel 0
I2S1_8CH Configuration
6.2.2 PDMs

The RK3308 provides a standard PDM interface that only supports master receive mode and offers 16-24 bit sampling accuracy and a sampling rate of up to 192K z. The PDM interface consists of one CLK output interface and four SDI input interfaces and supports eight PDM MIC inputs.

The PDM interface is multiplexed via 10MUX to PDM_M0, PDM_M1, and PDM_ 2. PDM_M0 and PDM_M1 are in the RK3308 VCCI01 power domain, while PDM2 is in the RK3308 VCCI02 power domain. Multiplexing into three groups provides users with greater flexibility in product design, allowing them to select the most suitable option based on their product’s functional requirements and the easiest layout solution to implement.

rk3308 m1 module
RK3308 PDM_M0&PDM_M1 Module
rk3308 m2 module
RK3308 PDM_M0&PDM_M2 Module
Signal Internal Pull up/Down Connection Method Description
PDM_8CH_CLK Pull Down Series with 22ohm resistor PDM_8CH_M0 system clock output
PDM_8CH_ SDI0_M0 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 0
PDM_8CH_ SDI1_M0 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 1
PDM_8CH_ SDI2_M0 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 2
PDM_8CH_SDI3_M0 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 3
PDM_M1
PDM_8CH_CLK_M1 Pull Down Series with 22ohm resistor PDM_8CH_M1 system clock output
PDM_8CH_ SDI0_M1 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 0
PDM_8CH_CLK_M_M2 Pull Down Series with 22ohm resistor
PDM_8CH_CLK_S_M2 Pull Down Series with 22ohm resistor
PDM_8CH_ SDI0_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 0
PDM_8CH_ SDI1_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 1
PDM_8CH_ SDI2_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 2
PDM_8CH_SDI3_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 3
6.2.3 SPDIF Digital Audio
Signal Internal Pull up/Down Connection Method Description
PDM_8CH_CLK_M_M2 Pull Down Series with 22ohm resistor PDM_8CH_M2 system clock output.
PDM_8CH_CLK_S_M2 Pull Down Series with 22ohm resistor PDM_8CH_M2 system clock output.
PDM_8CH_ SDI0_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 0
PDM_8CH_ SDI1_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 1
The CLK can be turned off during sleep
PDM_8CH_ SDI2_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 2
This CLK is a constant output and cannot be turned off.
PDM_8CH_SDI3_M2 Pull Down Series with 22ohm resistor PDM_8CH_M0 data input channel 3

SPDIF RX/TX
The RK3308 has a set of SPDIF interfaces that support both SPDIF input and output functions. It supports 16-bit, 20-bit, and 24-bit resolutions and can support a maximum sampling rate of 192Kz. The RK3308 SPDIF TX/RX interface signals are shown in the Figure:

rk3308 tx rx interface
RK3308 SPDIF_TX/RX Interface
6.3 Analog Microphone Circuit

The reference circuits for a condenser microphone and an electret microphone are shown in the following. Note that the circuit on the left side of the dashed Line should be placed close to the ADC, while the circuit on the right side must be placed close to the microphone.

Additionally, because microphones in speech products require an open design, ESD devices are added to the microphone circuit to System electrostatic discharge (ESD) capability, and they should be placed close to the microphone.

analog microphone circuit
Analog Microphone Circuit
6.4 I2S Microphone Circuit

The I2S microphone requires the RK3308 to provide the I2S_SCLK (bit clock) and I2S_LRCK (frame clock) signal. The data DIN pins of the two I2S microphones are connected to the same I2S_SDI Line of the RK3308, indicating that one data line can transmit left and right channel data. 

SELECT = low level indicates that the transmitted data is the left channel, and SELECT = high level indicates that the transmitted data is the right channel. 

When designing, the left and right channel levels should be set correctly according to the
microphone layout. The I2S register of the RK3308 has a polarity configuration bit that can invert the left and right polarities.

Due to the opening design required for microphones in the form of voice products, ESD devices
need to be added to the I2S_SCLK and L2S_I2S lines to impSystem’sSystem’ss antistatic capability. When laying out the design, ESD devices should be placed near the microphone

i2s digital microphone circuit
I2S Digital Microphone Circuit
6.5 PDM Microphone Circuit

The PDM microphone requires the RK3308B to provide the PDM_CLK sign l. The DATA pins of the two PDM microphones are connected to the same PDM_SDI Line of the RK3308B, indicating that one data line can transmit left and right channel da a. The corresponding left and right channels of the two microphones can be set using a signal pin (such as the L/R signal in Figure 6.5- ). Different PDM microphone manufacturers may have different high and low levels for the left and right channels, so the settings should be based on the microphone specifications.

When designing, the left and right channel levels should be set correctly according to the microphone layout. The PDM register of the RK3308B has a polarity configuration bit that can invert the left and right polarity. Due to the opening design required for microphones in the form of voice products, ESD devices need to be added to the PDM_CLK and PDM_SDI lines to system antistatic capability. When laying out the design, ESD devices should be placed near the microphone

pdm microphone circuit
PDM Microphone Circuit
6.6 Analog Power Amplifier Feedback Circuit

Voltage divider acquisition circuit When users use the following acquisition circuit, it is required that the output of the Class D amplifier must be connected to the LC circuit, as shown in Figure Analog Recovery Circuit 1. 

Taking the P-end as an example, Ra and Rc are mainly used to divide the output signal of the speakr. After the voltage is divided, it is input to the ADC of the RK3308B through a DC-blocking capacity. The DC component should be less than 500 V. That is, the DC voltage at point A should be less than 500mV

analog amplifier recovery circuit
Analog Amplifier Recovery Circuit 1

Second-order Filtering Acquisition Circuit
As shown in Figure 6.6-2, when the user’s Class D amplifier output does not use an LC filter circuit, an RC second-order filtering acquisition circuit can be used. The RC acquisition circuit and the DC￾blocking capacitor of the host end form a 22Hz-22KHz band-pass filter. Taking the P-end as an example, Ra and Rc are mainly used to divide the output signal of the speak r. After the voltage is divided, it is input to the ADC of the RK3308B through a DC-blocking capacity. The capacity ponent should be less than 500 V. That is, the DC voltage at point A should be less than 500 V. When modifying the voltage division according to different power amplifiers, it is recommended to modify the resistance value of a. The cutoff frequency of the first-stage RC filtering and the second￾stage RC filtering circuit is approximately 22KHz, and the formula for calculating the cutoff frequency is as follows:

sencond order

Where R is the parallel value of Ra and Rc when calculating the cutoff frequency of the first-stage RC filter.

analog amplifier recovery
Analog Amplifier Recovery Circuit 2
6.7 SDMMC Circuit

RK3308B provides an SDMMC interface controller that supports the SDMMC 3.0 protocol, as shown in the following Figure:

sdmmc module circuit
SDMMC Module Circuit
  • The SDMMC controller is powered by a separate power domain
  • SDMMC and UART2 functions are multiplexed together, with UART2 being the default debug port
  • VCCIO_SDMMC is the IO power supply and requires an external 3.3V power supply (SD 2.0 mode) or a 3.3V/1.8V adjustable power supply (SD3.0 mode)
Signal Internal Pull up/Down Connection Method Description
SDMMC_D[3:0] Pull Up Series with 22ohm resistor
The routing can be removed temporarily for shorts
SD data transmission and reception
SDMMC_CLK Pull Down Series with 22ohm resistor SD clock signal transmission
SDMMC_CMD Pull Up Series with 22ohm resistor
The routing can be removed temporarily for shorts
SD command transmission and reception
SDMMC Circuit Design
6.8 SDIO/UART Circuit

RK3308B supports WIFI/BT modules with SDIO 3.0 interface, as shown in the following Figu e. When using WIFI/BT modules with SDIO and UART interfaces, it is essential to note that the power supply of the RK3308 SDIO and UART controllers must match the IO level of the module.

rk3398 sdio uart module
RK3398_SDIO/UART Module
Signal Internal Pull up/Down Connection Method Description
SDI0_D[3:0] Pull Up Series with 22ohm resistor
The routing can be removed temporarily for shorts
SDI0 data transmission and reception
SDI0_CLK Pull Down Series with 22ohm resistor SDI0 clock signal transmission
SDI0_CMD Pull Up Series with 22ohm resistor
The routing can be removed temporarily for shorts
SDI0 command transmission and reception
SDI0 Circuit Design
Signal Internal Pull up/Down Connection Method Description
UART4_RX Pull Up Direct Connection UART4 data input
UART4_TX Pull Up Direct Connection UART4 data output
UART4_CTSN Pull Up Direct Connection UART4 allows signal transmission
UART4_RTSN Pull Up Direct Connection UART4 requests signal transmission
UART Circuit Design
6.9. USB

RK3308B has two USB 2.0 interfaces, as shown in the figure bel w. USB0 is the OTG interface, and USB1 is the HOST interface

usb circuit design
USB Circuit Design

When configuring the USB controller reference resistor R1400, please use 1% precision resistors, as it affects the USB amplitude and eye diagram quality.

usb extr

The 1.0V/1.8V power supply of the controller needs to be connected in series with a 1 ohm resistor to improve surge and ESD capability.

usb avdd

To improve USB performance, the decoupling capacitors of the controller power supply should
be placed close to the corresponding pins, such as C1401 and C1402, near the main control
pins

The USB data lines (DP/DM) are defaulted to be connected in series with 2.2 ohm resistor. To
suppress electromagnetic radiation, it is recommended to reserve a common mode choke on
the signal lines and use either a resistor or a common mode choke, depending on the actual
situation during debugging.

usb otg dm
6.10 RMII Circuit

RK3308B integrates a 100Mbps Ethernet MAC internally, which can be connected to different
Ethernet PHYs to achieve 100Mbps network functions. Please refer to the design documents of the PHY manufacturer for specific designs, and this guide will not go into too much detail. The working clock used by the PHY can be selected to be provided by an external crystal or by the MAC_CLK output of the RK3308B chip.

rmii circuit design
RMII Circuit Design

RK3308B supports 10/100M MAC, and the design and considerations for the 100M MAC section
are described as follows:

Signal Internal Pull up/Down Connection Method Description
MAC_CLK pull down 22ohm resistor in series MAC master clock output
MAC_TXD[2:0] pull down The 22ohm resistor in series can be deleted when the wiring is short Data transmission
MAC_RXD[2:0] pull down The 22ohm resistor in series can be deleted when the wiring is short Data reception
MAC_TXEN pull down direct connection Enable send data
MAC_RXDV pull down direct connection Receive data valid indicator
MAC_MDC pull down direct connection Configure interface clock
MAC_MDIO pull down direct connection Configure interface I/O

Reset: The MAC reset to the PHY is controlled by GPIO, or RC hardware reset circuit. It should be
noted that if using an RC hardware reset circuit, the power supply of PHY must be controllable.

gpio0 b2 tsadc shut

Transmission of control and status information between the MAC layer and PHY is done via the
MDIO interface, which includes the clock MDC signal and the data MIDO sign l. It should be noted that the MDIO signal needs to be pulled up, as shown in the diagram below:

vcc rmii
6.11. LCDC Circuit

The RK3308B LCDC interface has an 18-bit data signal LCDC_D0~LCDC_D17, which can support RGB/MCU screens.

rk3308b lcdc module
RK3308B LCDC Module

The corresponding LCDC signal connection relationship for using 18/24bit RGB screens and
8bit/16bit MCU screens is as follows:

rk3308 lcdc
The RK3308B LCDC signals correspond to the RGB distribution
6.12 SARADC Circuit

RK3308B has 6 channels of SARADC with a power supply voltage of 1.8V and a sampling precision of 10 bits. The SARADC’s ADC_IN1 is used as the default function key input, and the input circuit is designed as shown in the following Figur s. The essential input value can be set by adjusting the voltage divider ratio, and it is recommended to have a minimum interval of 35 between any two key values.

ADC_IN1 also use the System upgrade button input, as shown in the first button of SARADC Button Sampling Circuit, which is the VOL+/Recovery button in regular system operation. It is only used as the Recovery mode during initial power- n. Specifically, with the firmware already burned Systemhe system, Systemhe system starts up; press and hold the VOL+/Recovery button to pull ADC_IN1 low, keeping it at a 0V level (not exceeding 100mV), and RK3308B will enter Rockusb firmware update mo e. When the PC recognizes the USB device, release the button to restore ADC_IN to a high level (1.8V) to perform the firmware update.

rk 3308b saradc module
RK3308B SARADC Module
rk3308b saradc button sampling circuit
RK3308B SARADC Button Sampling Circuit

NOTE
The ADC_KEY_IN1 signal in the red box in Figure SARADC Button Sampling Circuit must be pulled up.

6.13 UART Debug Circuit

The RK3308B platform defaults to using UART2_M1 as the serial port for debugging, as shown in Figure 6.13-1.
UART2 is also connected to UART2_M0 through the internal IOMUX, as shown in Figure 6.13 2. UART2_M0 and UART2_M1 can only be used one at a time.
UART2_M1 is multiplexed with the SDMMC interface, so if the SDMMC interface is used on the product and a TF card is needed, UART2_M1 cannot be used. Therefore, it is recommended to reserve UART2_M0 for debugging in case the SDMMC interface function is used and switch to UART2_M0 for debugging through software modification, as shown in the design of Figure RK3308B UART_M1

rk3308b uart2 m1
RK3308B UART2_M1
rk3308b uart2 m0
RK3308B UART2_M0
compatibility design rk3308b uart debug
Compatibility Design for RK3308B UART Debug

GPIO Circuit description power supply pins in the GPIO power domain are as follows

Power Domain GPIO Type Pin Name Description
VCCIO0 (PMUIO) 1.8V/3.3V VCCIO0 Default 3.3V power for this domain (group of) GPIO.
VCCIO1 1.8V/3.3V VCCIO1 1.8V or 3.3V power for this domain (group of) GPIO.
VCCIO2 1.8V/3.3V VCCIO2 1.8V or 3.3V power for this domain (group of) GPIO.
VCCIO3 1.8V/3.3V VCCIO3 1.8V or 3.3V power for this domain (group of) GPIO.
VCCIO4 1.8V/3.3V VCCIO4 1.8V or 3.3V power for this domain (group of) GPIO.
  • In RK3308B, GPIO can be configured as 1.8V or 3.3V level depending on the actual application. The software must be configured accordingly based on the selected voltage level.
  • All GPIOs in RK3308B support interrupt functions.
  • The pull-up and pull-down status of RK3308B’s GPIOs can be configured and disabled after power- n. In the schematic package, those marked with “_d” are the default internal pull-downs after power-on, while those marked with “_u” are the default internal pull-ups after power-on, as shown in the Figure below.
gpio0 a0 a1 a2 a3

The GPIO drive capability provides four adjustable levels of drive strength: 2mA, 4mA, 8mA,
and 12 A. The initial default drive strength for each GPIO type is different. Please refer to the
chip datasheet for configuration modification

7 Product Dimensions

dsom 050r dimensions front
dsom 050r dimensions back
Item Parameter
Exterior Stamp Hole
Core Board Size 45mm x 40.2mm x 3.35mm
Pin Spacing 1.2 mm
Pin Pad Size 1.5mm x 0.7mm
Number of Pins 136Pins
Number of Layers 6 floors
Warpage less than 0.5 %

8 The methods of Coreboard Thermal Control

8.1 Thermal Control Strategy

There is a generic thermal system driver framework in the Linux kernel that defines a number of temperature control strategies. The following three strategies are currently in common use:

  • Power_allocator: Introduces proportional-integral-derivative (PID) control, dynamically allocates power to each module based on the current temperature and converts power to Frequency to achieve Frequency limiting based on temperature.
  • Step_wise: Limits the Frequenof in steps based on the current temperature.
  • User space: Does not limit Frequency.

The RK3328 chip has a T-sensor that detects the chip’s internal temperature and uses the Power_allocator strategy by default. The operating states are as follows:

  • If the temperature exceeds the set temperature value:
    ·  If the temperature trend is rising, the Frequency is gradually reduced.
    ·  If the temperature trend is falling, the Frequency is gradually increased.
  • When the temperature falls to the set temperature value:
    ·  If the temperature trend is increasing, the Frequency remains unchanged.
    ·  If the temperature trend is falling, the Frequency is gradually increased.
  • Suppose the Frequency reaches its maximum and the temperature is still below the set valve. In that case, the CPU frequency is no longer under thermal control, and the CPU frequency becomes system load frequency modulation.
  • If the chip is still overheating after the Frequency has been reduced (e.g., due to poor heat dissipation) and the temperature exceeds 95 degrees, the software will trigger a restart t. If the restart fails due to deadlock or other reasons and the chip exceeds 105 degrees, the otp_out inside the chip will trigger an immediate shutdown by the PMIC.

Note: The temperature trend is determined by comparing the previous and current temperaturesIf the device temperature is below the threshold, the temperature is sampled every l seconds; if the device temperature exceeds the threshold, the temperature is sampled every 20ms, and the Frequency is limited.

8.2 Thermal Control Configure

The RK3328 SDK provides separate thermal control strategies for the CPU and G U.
Please refer to the (Rockchip_Developer_Guide_Thermal) document for specific configurations.

9 Production Guide of DSOM-050 RK3308 SOM

9.1 SMT process

Select modules that can be SMT or in-line packaged according to the customer’s PCB design. If the board is designed for SMT packaging, use SMT-packaged modules. If the board is designed for in line assembly, use in-line assembly y. Modules must be soldered within 24 hours of unpacking. If not, place them in a dry cabinet with a relative humidity of no more than 10% or re-pack them in a vacuum and record the exposure time (total exposure time must not exceed 168 hours).

Instruments or equipment required for SMT assembly:

  • SMT Mounter
  • SPI
  • Reflow soldering
  • Oven temperature tester
  • AOI

 

Instruments or equipment required for baking:

  • Cabinet ovens
  • Antistatic high-temperature trays
  • Antistatic and high-temperature gloves
9.2 Module storage conditions:

Moisture-proof bags must be stored at a temperature <40°C and humidity <90%H. Dry-packed products have a shelf life of 12 months from the date of sealing of the package—sealed packaging with a humidity indicator card.

image41
9.3 Baking is required when:

The vacuum bag is found to be broken before unpacking.
After unpacking, the bag is found to be without a humidity indicator card.
The humidity indicator card reads 10% or more after unpacking, and the color ring turns pink.
Total exposure time after unpacking exceeds 168 hours.
More than 12 months from the date of the first sealed packaging.

Baking parameters are as follows:

Baking temperature: 60°C for reel packs, humidity less than or equal to 5% RH; 125°C for tray packs, humidity less than or equal to 5% RH (high-temperature-resistant trays, not blister packs for tow trays).

Baking time: 48 hours for reel packaging; 12 hours for pallet packaging.

Alarm temperature setting: 65°C for reel packs; 135°C for pallet packs.

After cooling to below 36°C under natural conditions, production can be carried out.

If the exposure time after baking is greater than 168 hours and not used up, bake again.

If the exposure time is more than 168 hours without baking, it is not recommended to use the reflow soldering process to solder this batch of modules. The modules are class 3 moisture-sensitive devices and may become damp when the exposure time exceeds d. 

This may lead to device failure or poor soldering when high-temperature soldering is carried out.

9.4 ESD

Please protect the module from electrostatic discharge (ESD) during the entire production process.

9.5 Conformity

To ensure product qualification rates, it is recommended to use SPI and AOI test equipment to monitor solder paste printing and placement quality.

9.6 Recommended Furnace Temperature Profile

Please follow the reflow profile for SMT placement with a peak temperature of 245C. The reflow temperature profile is shown below using the SAC305 alloy solder paste.

image42

Description for graphs of curves.
A: Temperature axis
B: Time axis
C: Alloy liquid phase line temperature: 217-220°C
D: Slope of temperature rise: 1-3°C/s
E: Constant temperature time: 60-120s, constant temperature: 150-200°C
F: Time above liquid phase line: 50-70s
G: Peak temperature: 235-245°C
H: the slope of temperature reduction: 1-4°C/s
Note: above-recommended curves are based on SAC305 alloy solder paste as an example. Please set the recommended oven temperature curve for other alloy solder pastes according to the solder paste specification.

9.7 Storage
image43
9.8 Order Information
Model RAM eMMC
DSOM-050R-J 512MB 8GB
DSOM-050R-G 256MB 4GB

Documentations

DusunIoT offers full set of development resources including QUICK START, SDK, Firmware packaging, module firmware, Tools, vairous third party software,etc.

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