DSOM-090M MediaTek MT7621 System on Module

The DSOM-090M System on Module (SOM) core board is equipped with MTK’s MT7621A processor supporting OpenWRT OS, which includes a dual-core MIPS1004Kc running at a maximum clock speed of 880MHz.
Table of Contents
dsom 090m

1. DSOM-090M MediaTek MT7621 SOM Introduction

1.1 System on Module Purpose& Description

The MT7621 System on Module is equipped with MTK’s MT7621A processor, which includes a dual-core MIPS1004Kc running at a maximum clock speed of 880MHz. Its capabilities make it well-suited for various applications, including Internet service routers, wireless routers, home security gateways, NAS services, and switch control processors.

The MT7621 System on Module is a versatile and powerful platform for developing networking and security solutions. The dual-core architecture enables efficient multitasking and handling of complex network traffic. It can be customized and configured to meet the specific needs of a wide range of applications, from small home networks to large enterprise deployments.

With its robust hardware and advanced features, the MT7621 System on Module is an excellent choice for developers and system integrators looking to build high-performance, reliable, and secure network solutions.

1.2 System on Module Product Feature Summary
  • Size 65mm x 69mm x 2.5mm, featuring sufficient GPIO interfaces
  • eMMC up to 8GB
  • RAM up to 512MB
  • SPI FLASH up to 64MB
  • Supports OpenWRT OS
  • Supports wireless LAN standards: IEEE 802.11 a/b/g/n/ac
  • Frequency range: 2.4GHz~2.4835GHz or 5.18GHz~5.825GHz
  • Wireless rate: 300Mbps for 2.4GHz~2.4835GHz frequency range and 866.7Mbps for 5.18GHz~5.825GHz frequency range
  • The operating temperature range of the core module is 0~55 degrees
  • ROHS certified
  • The product is stable and reliable and will operate normally through repeated High/Low Temperature Testing and Restarts Testing.
1.3 System on Module Application
  • Routers
  • NAS Devices
  • iNICs (Intelligent Network Interface Cards)
  • Dual Band Concurrent Band
  • Home Security Gateway

2. Main chip block diagram of DSOM-090M MediaTek MT7621 SOM

2.1 Main Chip Block Diagram
DSOM-090M Main Chip Block Diagram
2.2 Core Board Block Diagram
DSOM-090M Core Board Block Diagram

3. Basic Parameters and Interfaces of DSOM-090M MediaTek MT7621 SOM

3.1 Basic Parameters
ItemParameter
CPUMIPS 1004Kc(800MHz), I-Cache, D-Cache 32KB, 32KB, L2 Cache 256KB
RAMDDR3L 512MB (128MB, 256MB optional)
MemoryeMMC 8GB( 4GB, 16GB optional)
Wireless StandardIEEE 802.11 a/b/g/n/ac
Operating Frequency2.4 GHz ~ 2.4835 GHz or 5.18GHz ~ 5.825GHz
ModulationIEEE 802.11b: CCK, DQPSK, DBPSK
80211g/a: 64-QAM,16-QAM, QPSK, BPSK
802.11n: 64-QAM,16-QAM, QPSK, BPSK
802.11ac: 256-QAM,64-QAM,16-QAM, QPSK, BPSK
Wireless Transmit Rate802.11b: 1,2,5.5,11Mbps
802.11g: 6, 9, 12, 18, 24, 36, 48, 54Mbps
802.11n: MCS0~7, HT20 reach up to 72.2Mbps, HT40 reaches up to 150Mbps,
HT40 reach up to 300Mbps (2T2R)
802.11ac: VHT20 reach up to 173.3Mbps, VHT40 reach up to 400Mbps
VHT80 reaches up to 866.7Mbps
Wireless EncryptionWEP/ TKIP/ WPA/ WPA2
Operation VoltageDC12V/1.5 ( Recommend)
OSOpenWRT
TemperatureOperating Temperature: 0° C ~85 °C
Storage Temperature: -40 °C ~85 °C
Humidity10~90%(Non-condensing)
Barometric Pressure76Kpa ~ 106Kpa
Size38mm × 38mm
PCB Dimension65mm x 69mm x 2.5mm
3.2 Interfaces
ItemParameter
Audio1 x PCM, 1 x I2S
eMMCThe onboard interface for eMMC is exposed through pins but should be left unconnected (floating) when not used externally.
Ethernet4 x GEPHY, 1 x RGMII
USB2.01 x USB 2.0
USB3.01 x USB 3.0
UART3 x UART (UART for Debugging, UART2,a nd UART3 supports Flow Control )
I2C1 x I2C
JTAG1 x JTAG
MDC/MDIO1 x MDC/MDIO
LED ControlSix LED control pins in total: four for the GEPHY interfaces and two to indicate the operating status of the 2.4GHz and 5GHz modes of the Wi-Fi connection.

4. Pin Definition of DSOM-090M MediaTek MT7621 SOM

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PinNameType II/O DefI/OI/O Driv. (mA)I/O Voltage(V)Functions
1JTMS/GPIO15I/OIdown43.3JTAG Mode Select OR GPIO 15
2JTDI/ GPIO14I/OIdown43.3JTAG Data Input OR GPIO 14
3JTRST_N/ GPIO17I/OIdown43.3JTAG Target Reset OR GPIO 17
4JTDO/ GPIO13I/OOdown43.3JTAG Data Output OR GPIO 13
5JTCLK/ GPIO16I/OIdown43.3JTAG Clock OR GPIO 16
6LED_WLAN_2.4GI/OOdown143.3WIFI 2.4GHz status LED indicators
7LED_WLAN_5GI/OOup163.3WIFI 5GHz status LED indicators
8ESW_P3_LED_0I/OIN/A43.3Port 3 PHY LED indicators
9ESW_P0_LED_0I/OIN/A43.3Port 0 PHY LED indicators
10ESW_P1_LED_0I/OIN/A43.3Port 1 PHY LED indicators
11ESW_P2_LED_0I/OIN/A43.3Port 2 PHY LED indicators
12D2DB_PORST_NIIN/A43.3Power on reset
........................

NOTE:
I/O Types: I = digital-input, O = digital-output, I/O = digital input/output (bidirectional)
A=Analog IO, P = power supply, Def default IO direction for digital IO
All GPIO pins support interrupts.

5. Electrical Parameters of DSOM-090M MediaTek MT7621 SOM

5.1 Absolute Electrical Parameters
ParameterDescriptionMinMaxUnit
VCC12V0_SYSVCC12V0_SYS Input voltage-0.312.6V
TaOperating temperature range055
TsStore temperature range-4085

Note: Exposure to conditions beyond the absolute maximum ratings may cause permanent damage and affect the reliability and safety of the device and its systems. The functional operations cannot be guaranteed beyond specified values in the recommended conditions.

5.2 General Operation Conditions
ParameterDescriptionMinTypMaxUnit
VCC12V0_SYSVCC12V0_SYS Input voltage11.41212.6V
VCC5V0_SYS Supply CurrentVCC5V0_SYS Input current1.251.5A
TaOperating temperature range02555
TsStore temperature range-402585

6. RF-Performance of DSOM-090M MediaTek MT7621 SOM

6.1 2.4G RF-Performance
ModeRate
(Mbps)
Power(dBm) +1.5dBmEVM(dB) +2dBSensitivity(dBm) +2dBm
CH1CH7CH13CH1CH7CH13CH1CH7CH13
11b117.517.517.5-24.5-24.5-24.5-96-96-96
1117.517.517.5-23.2-23.2-23.2-85-85-85
11g917.517.517.5-30.8-30.8-30.8-87-87-87
5417.517.517.5-31-31-31-69-69-69
ModeRate
(Mbps)
Power(dBm) +1.5dBmEVM(dB) +2dBSensitivity(dBm) +2dBm
CH3CH7CH11CH3CH7CH11CH3CH7CH11
11n
HT40
MCS014.514.514.5-31.2-31.2-31.2-87-87-87
MCS714.514.514.5-30.8-30.8-30.8-68-68-68
6.2 5G RF-Performance
ModeRate
(Mbps)
Power(dBm) ±1.5dBmEVM(dB) ±2dBSensitivity(dBm) ±2dBm
CH36CH
100
CH
140
CH
161
CH36CH
100
CH
140
CH
161
CH
36
CH
100
CH
140
CH
161
11a918.218.218.218.2-31-31-31-31-89-89-89-89
5418.218.218.218.2-31-31-31-31-73-73-73-73
ModeRate
(Mbps)
Power(dBm) ±1.5dBmEVM(dB) ±2dBSensitivity(dBm) ±2dBm
CH38CH
102
CH
142
CH
159
CH38CH
102
CH
142
CH
159
CH
38
CH
102
CH
142
CH
159
11n
HT40
MCS017.517.5-30-87-87-87
17.517.517.517.5-31-31-31-31-69-69-69-69
CH
42
CH
106
CH
138
CH
155
CH
42
CH
106
CH
138
CH
155
CH
42
CH
106
CH
138
CH
155
11acMCS016.516.516.516.5-30.5-30.5-30.5-30.5-84-84-84-84
MCS716.516.516.516.5-33.5-33.5-33.5-33.5-57-57-57-57

7. Hardware Design Guidelines of DSOM-090M MediaTek MT7621 SOM

7.1 JTAG Interface
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The JTAG interface of the MT7621 chip includes the JTMS, JTDI, JTRST_N, JTDO, and JTCLK pins. The JTAG circuit on the MT7621 System on Module is shown in the above diagram. This interface can be used to debug the MT7621 chip with an external JTAG tool, but it is generally not needed. Several pins in the JTAG interface can be used as GPIO.

7.2 UART Interface
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The MT7621A chip provides three UART interfaces. In addition to UART1, both UART2 and UART3 have flow control functions. All three UART interfaces can be multiplexed as GPIO, but the RXD, TXD, CTS, and RTS pins of UART2 and UART3 can only be used as a whole for either UART or GPIO functions. The UART2 interface can also be multiplexed as a PCM audio interface, and the UART3 interface can also be multiplexed as an I2S audio interface.

The TXD1 pin of UART1, TXD2, and RTS2_N pins of UART2 and RTS3_N pin of UART3 on the core board have pull-up/down resistors as mode configuration options during chip startup.

7.3 USB Interface

The MT7621A chip has one set of USB 2.0 interfaces and one set of USB 3.0 interfaces. Please note when designing the carrier board:

  • USB 2.0 and USB 3.0 interfaces are typically used in Host mode for external
    connectivity.
  • It is recommended to reserve a common mode choke on the signal line to
    reduce electromagnetic interference. During debugging, resistors or additional
    common mode chokes may be used as needed.
  • USB 2.0 Board Design and Layout Guidelines
    Differential pair intra-pair skew less than 10 mils
    Differential pair trace length less than 3 inches
    Differential pairs have less than 3 through-holes for layer changes
    Differential pair impedance controlled to 90 ohms +/-10%.
    Differential pairs are spaced using the 3W rule with other signals
  • USB 3.0 Board Design and Layout Guidelines
    Differential pair intra-pair skew less than 5 mils
    Differential pair trace length less than 3 inches
    Differential pairs have less than 2 through-holes for layer changes
    Differential pair impedance controlled to 90 ohms +/-10%.
    Differential pairs are spaced using the 3W rule with other signals
    l It is necessary to consider the design of protection circuits on the USB circuit
    during the PCB design to meet ESD protection requirements. To avoid the effect
    of the protection device on the USB signal and to achieve a good protection
    effect, the following principles are recommended for the Coreboard design:
  • The ESD protection device is recommended to be placed close to the USB
    connector port.
  • The ESD protection device is recommended to be an air 15kV, contact 8kV
    device with a response time of less than 1ns.
  • USB 2.0 has a transmission speed of 480Mbps, so the differential signal is very
    sensitive to parasitic capacitance on the line. Therefore, ESD protection devices
    with low parasitic capacitance should be selected, with a capacitance of less
    than 1pF.
  • USB 3.0 has a transmission speed of 5Gbps, so the differential signal is very
    sensitive to parasitic capacitance on the line. Therefore, ESD protection devices
    with low parasitic capacitance should be selected, with a capacitance of less
    than 0.4pF.
  • The 2.2 Ohm resistor in series with the USB signal cannot be modified or
    omitted
7.4 Audio Interface

The MT7621A features two audio interfaces: PCM and I2S. The PCM audio interface is multiplexed with the UART2 interface, while the I2S audio interface is multiplexed with the UART3 interface.

  • PCM
    The correspondence between the PCM audio interface pins and the UART2 interfacepins is as follows
Pin For PCM InterfacePin For UART InterfaceDescription
PCM_DTXRTS_NPCM data output
PCM_DRXCTS_NPCM data input
PCM_CLKTXDThe PCM clock, also known as the Pulse Code Modulation clock, can be configured to operate at any clock rate between 256k and 8.192MHz.
PCM_FSRXDPCM data frame synchronization
  • I2S
    The correspondence between the I2S audio interface pins and the UART3 interface
    pins is as follows:
Pin For I2S InterfacePin For UART3 InterfaceDescription
I2S_SD0RTS_NPCM data output
I2S_CLKCTS_NThe I2S clock
I2S_WSTXDI2S channel selection (bit selection)
I2S_SDIRXDI2S data frame synchronization
7.5 I2C Interface

The MT7621A has an I2C interface with a maximum speed of 100KHz. Please note that the clock and data pins of the I2C interface on the System on Module are not connected to pull-up resistors, so external pull-up resistors are required in the design. The resistance value of the pull-up resistors should be selected based on the speed used.

7.6 Gigabit Ethernet PHY

The MT7621 System on Module has four Gigabit Ethernet PHY interfaces, each with the same function. These interfaces are integrated into the MT7621A chip.

The PCB design guidelines for ESW_TXVP_A_P0, ESW_TXVN_A_P0, ESW_TXVP_B_P0, ESW_TXVN_B_P0, ESW_TXVP_C_P0, ESW_TXVN_C_P0, ESW_TXVP_D_P0 and ESW_TXVN_D_P0 are as follows:
Differential pair trace length less than 3 inches
Differential pairs have less than 2 through-holes for layer changes
Differential pair impedance controlled to 100 ohms +/-10%.
Differential pairs are spaced using the 3W rule with other signals

7.7 RGMII/MII Interface

The MT7621A chip has an RGMII/MII interface. MDC and MDIO are used to configure external Ethernet chips.
Note:
When controlling external/internal PHY, MDC/MDIO cannot be used as GPIO; When the total bandwidth of WAN/LAN reaches 2Gbps, the GPIO function on GE2 cannot be used. Leave the pin floating.

  • The Design Guidelines for RGMII/MII interfaces are as follows:
ItemDesign Rules
Single-ended trace impedance requirement50Ω ± 10%
TXD0, TXD1, TXD2, TXD3, TXEN, and TXCLK should have equal length<120mil
RXD0, RXD1, RXD2, RXD3, RXDV, and RXCLK should have equal length<120mil
The total length of PCB traces<5000mil
The gap between RGMII signals>=2 times the line width
The gap between RGMII signals and other signals>=3 times the line width
TXCLK and RXCLK routing requirementsmust be grounded throughout, grounded routing interval within 300mil must have ground overa hole
7.8 Radio Frequency Circuit

The MT7621 System on Module supports both 2.4GHz and 5GHz wireless functionality. It can be externally connected to two 2.4GHz antennas and one 5GHz antenna via IPEX sockets. The MT7603 chip is used to implement the 2.4GHz wireless functionality, and the MT7613 chip is used to implement the 5GHz wireless functionality on the core board. Both chips have shielding covers installed on top of them to enhance anti-interference performance and reduce external EMI radiation.

8. Product Dimensions of DSOM-090M MediaTek MT7621 SOM

Dimensions of DSOM-090M
Dimensions of DSOM-090M Behind
ItemParameter
ExteriorStamp Hole
Core Board Size65mm*69mm*2.5mm
Pin Spacing1.2mm
Pin Pad Size1.6mm*0.8mm
Number of Pins100 Pins
Warpageless than 0.5 %

9. The methods of Coreboard Thermal Control

The working environment temperature range for the core board is 0℃ to 55℃, so the maximum temperature inside the enclosure cannot exceed 55 degrees.

The MT7621 System on Module is equipped with a heat sink, and the overall size of the core board with the heat sink is 71.3mm × 65.8mm × 16.3mm. Sufficient heat dissipation holes are reserved in the structure when using the MT7621 core board for product design. The heat dissipation holes should allow air convection to dissipate heat from inside the enclosure. If possible, a fan should be used for better heat dissipation.

10. Production Guide of DSOM-090M MediaTek MT7621 SOM

10.1 SMT process

Select modules that can be SMT or in-line packaged according to the customer’s PCB design scheme. If the board is designed for SMT packaging, use SMT-packaged modules. If the board is designed for in-line assembly, use in-line assembly. Modules must be soldered within 24 hours of unpacking. If not, place them in a dry cabinet with a relative humidity of no more than 10% or re-pack them in a vacuum and record the exposure time (total exposure time must not exceed 168 hours).

Instruments or equipment required for SMT assembly:

  • SMT Mounter
  • SPI
  • Reflow soldering
  • Oven temperature tester
  • AOI

Instruments or equipment required for baking:

  • Cabinet ovens
  • Antistatic high-temperature trays
  • Antistatic and high-temperature gloves
10.2 Module storage conditions:

Moisture-proof bags must be stored at a temperature <40°C and humidity <90% RH. Dry-packed products have a shelf life of 12 months from the date of sealing of the package. Sealed packaging with humidity indicator card.

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10.3 Baking is required when:

The vacuum bag is found to be broken before unpacking.

After unpacking, the bag is found to be without a humidity indicator card.

The humidity indicator card reads 10% or more after unpacking, and the color ring turns pink.

Total exposure time after unpacking exceeds 168 hours.

More than 12 months from the date of the first sealed packaging.

Baking parameters are as follows:
Baking temperature: 60°C for reel packs, humidity less than or equal to 5% RH; 125°C for tray packs, humidity less than or equal to 5% RH (high-temperature-resistant trays, not blister packs for tow trays).
Baking time: 48 hours for reel packaging; 12 hours for pallet packaging.
Alarm temperature setting: 65°C for reel packs; 135°C for pallet packs.
After cooling to below 36°C under natural conditions, production can be carried out.
If the exposure time after baking is greater than 168 hours and not used up, bake again.
If the exposure time is more than 168 hours without baking, it is not recommended to use the reflow soldering process to solder this batch of modules. The modules are class 3 moisture-sensitive devices and may become damp when the exposure time is exceeded. This may lead to device failure or poor soldering when high-temperature soldering is carried out.

10.4 ESD
Please protect the module from electrostatic discharge (ESD) during production.
10.5 Conformity

To ensure product qualification rates, it is recommended to use SPI and AOI test equipment to monitor solder paste printing and placement quality

10.6 Recommended Furnace Temperature Profile

Please follow the reflow profile for SMT placement with a peak temperature of 245°C. The reflow temperature profile is shown below using the SAC305 alloy solder paste.

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Description for graphs of curves.
A: Temperature axis
B: Time axis
C: Alloy liquid phase line temperature: 217-220°C
D: Slope of temperature rise: 1-3°C/s
E: Constant temperature time: 60-120s, constant temperature: 150-200°C
F: Time above liquid phase line: 50-70s
G: Peak temperature: 235-245°C
H: the slope of temperature reduction: 1-4°C/s
Note: The above-recommended curves are based on SAC305 alloy solder paste as
an example. Please set the recommended oven temperature curve for other alloy solder pastes according to the solder paste specification.

10.7 Storage
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10.8 Order Information
Product ModelRAMeMMC
DSOM-090M-I512 MB4 GB
DSOM-090M-J512 MB8 GB
10.9 Package
TBD

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